1. Field of the Invention
The invention relates to a fast locked all digital phase lock loop and control method thereof.
2. Description of the Related Art
All digital phase lock loop (PLL) technology is one of the major technological breakthroughs for wireless communication, because it may be implemented easier in system on chip (SOC) devices manufactured by advanced semiconductor process than the analog phase lock loop. However, designing an all digital PLL with features such as fast locking and low phase noise is challenging.
FIG. 1 is a schematic diagram of a conventional all digital phase lock loop viewed in the phase domain. Following, a digital phase lock loop is briefly introduced. However, for a more detailed description of the digital phase lock loop in FIG. 1, reference can be made to U.S. Pat. No. 7,145,399.
The phase error φE between the variable signal fv and reference signal fref can be determined by the phase detector 115. As shown in FIG. 1, the phase detector 115 has three inputs, where one input is provided by inputting the reference signal fref to the reference phase accumulator 105 and is regarded as the phase of the reference signal fref. Another input is provided by inputting the variable signal fv to the oscillator phase accumulator 140 and the sampler 145 and is regarded as the phase of the variable signal fv. The last input is the fractional phase error between the variable signal fv and reference signal fref. The sum of the three inputs is the phase error φE.
The loop filter 120 filters the phase error φE and/or adjusts the magnitude of phase error φE. The loop filter 120 generates an oscillator tuning word (OTW) to modify the output of a digitally controlled oscillator (DCO) 125, i.e. the variable signal fv.
In the current design of the all digital phase lock loops, gear shift mechanism and type II and higher order loop filters are utilized for achieving the purposes of fast locking and low phase noise. In U.S. Pub. No. 2003/0234693, an all digital phase lock loop is disclosed.
However, designers still must design an adaptive all digital phase lock loop.